WALLACE TREE MULTIPLIERThere are various ways to perform the multiplication operation by mean of hardware as well as the software. This mechanism indirectly depends on cost in addition to the budget cost of the transistors to perform the specific procedure. In early phases of digital development critical or complex computations are performed in software. Later on partial hardware support was sheltered. Today high processing units perform a crucial role in order to satisfy the user need. Standard operation involves the shifting coupled with the addition operation.

Linear multiplier is the most common practice multiplier due to its reliability as well as common practice layout. Implementation of multiplier includes Accumulator as well as the shifter in order to carry addition of partial product. It is common practice to carry one partial product for each cycle. In most of the advanced multiplier architecture adopt the algorithm often known as Baugh-Wooley algorithm. 4×4 Multiplier is put into practice by utilizing the combinational circuits that includes Full Adder in addition to the AND Gates.

Since if we consider the four-bit multiplier N and multiplicand as M then sequence can be written as N: n3, n2, n1, n0and M: m3, m2, m1, m0. The main purpose of implementing the multiplier with aid of ROM due to manufacturing cost is less when compared to another approach. At the same, time efforts made to design the component is bare minimum.3.1 Types of MultipliersBasically multipliers organization are classified into different categories but mainly three different multipliers got huge importance due to their architecture and they are: Serial Multiplier Parallel Multiplier and Serial Parallel Multiplier3.1.1 Serial multiplierThese types of multiplier are operated by utilizing the algorithm of successive addition. Furthermore, mainly addition algorithm is simple in composition and operands are penetrating in serial manner. Due to its reliability, physical circuits involve a reduced amount of hardware for their realization in addition to the diminished area of chip. Even though multiplier has reduction in area, the time required to process the data is very high, since the operands enter in a serial manner.3.1.2 Parallel multiplierThere are mainly three decisive factor are considered while designing the multipliers and they are: (1) Area of the Chip (2) Computational Speed and (3) Power Consumption. Every advance designed multipliers utilizes the parallel multiplication in order to process the data with high speed. In current years, high speed processing parallel multipliers widely utilized in Reduced Instruction Set Computer (RISC), graphic accelerator, digital signal processing which is larger in the area as well as the complexity of design is very high. For an instance, Braun Multiplier, Baugh-Wooley multiplier and other parallel multipliers like Wallace tree multipliers requires larger area.3.1.3 Serial-Parallel MultipliersAlthough parallel multiplier has high computational speed, it requires a larger area that is not a good sign. For this reason, serial-parallel multipliers are utilized. Since it acts as better tradeoff between the serial multiplier that consume time and parallel multiplier which consume larger area for their implementation. In a serial multiplier, one of the operand is enter in serial manner while other one stored in parallel that has constant in number of bits. So, therefore as a result, the processing speed increases as well as consumes less area when compared to the parallel and serial multipliers.3.2 Braun MultiplierThe Braun multiplier was proposed by the author named as Braun Edward Louis. This multiplier is one of the finest parallel multiplier that have reliable in structure. Braun Multiplier is also known as Carry Save Array Multiplier and multiplier can execute the multiplication operation on two unsigned numbers. Braun multiplier mainly accomplishes AND gate array as well as the adders is organized in such a way that it has iterative in arrangement. Braun multiplier does not require logic register for their arrangement and such multiplier commonly called as non-additive multiplier. The Braun Multiplier of n x n’-bit involves n(n-1) adders that means it has to perform n(n-1) additions and also involves 2 number of AND gates. That means the multiplier perform 2 number of computations in order to process the output. Braun multiplier is one of the efficient and reliable multiplier often utilized in layout design because it offers better flexibility when compared to other multipliers. Its internal organization mainly consists of bank of full adders and often realized in the application of Very Large Scale Integration (VLSI) circuits as well as Application Specific Integrated Circuits.3.3 Booth MultiplierBooth multiplier is performed by utilizing booth multiplication algorithm. It can perform operation on 2’s complement signed number. Booth algorithm was developed and implemented by Andrew Donald Booth in the year 1950. This algorithm is performed by frequent addition of predetermined numbers so as to produce partial products P. consequently performing the right shift operation. Since Booth multiplier is frequently utilized for signed numbers for the purpose of high speed processing. The multiplier and multiplier operated to form a partial product. In this booth multiplier partial product is generated by mean of Booth encoder as well as Booth decoder. By utilizing radix two structures in favor of multiplier the overall number of partial products can be diminished to N/n. furthermore computation speed has been increased to great extent. Booth multiplier has great significance due to its reliability and faster computation. Furthermore, area required to implement this architecture is very less.3.4 Baugh-Wooley MultiplierBaugh-Wooley multiplier got huge importance due to its reliability while performing the multiplication with the signed bits. This multiplier is designed to carry out the multiplication of binary bits in two’s complement form. The power consumption as well as the area of the different multiplier architecture differs with the size of the operand in addition to layout planning. The escalating reliability as well as area at the level of silicon will diminishes the power consumption.3.5 Wallace tree multiplierWallace multiplier has some key advantages like reliable hardware implementation in digital circuits. This multiplier multiplies the two integers that have been designed by the well-known scientist named as Chris Wallace in the year 1964. The Wallace tree involves three fundamental steps. In the initial step is carried by multiplying the each bit of the one of the argument with every bit of the other argument that involves the 2 number of computations. In subsequent steps involves the reduction in partial product with half and full adder layers respectively. Consequently, cluster the wires into two individual numbers and processing the result with aid of conventional adder.The structure of Wallace tree has been entitled in figure.3.1. The key procedure involved in the computational procedure as follows. If more than three wires with the same weight, then input them every wire that has same weight into a full adder or else if two wires with identical weight then make them as input for the half adder and other dissimilar weights tie them to the next consequent layer. Then main advantage of Wallace tree is, it has only 3 number of reduction layers. Although full adder input has same magnitude but these inputs generate different time delay, since full adder is act like 3:2 compressor in Wallace tree. So that input as well as output should not be considered as the same